1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly to Dual Die Package (DDP) semiconductor packages having two semiconductor chips stacked.
2. Description of the Related Art
In these years, for small-sized electronic devices such as a cellular telephone, there is an increasing demand that a semiconductor package (semiconductor device) that is to be mounted on a circuit board be denser in order to meet the downsizing and increased functionality of devices. In order to meet this demand, semiconductor packages having a plurality of semiconductor chips stacked are conceived. For one example, Dual Die Package (DDP) semiconductor packages are known, in which two semiconductor chips are stacked on a package substrate (wiring board).
In many DDP semiconductor packages, as disclosed in JP 2001-85609 A and JP 2009-140995 A, for example, a semiconductor chip having an electrode pad row formed on one surface thereof is used for a semiconductor chip to be mounted. The electrode pad row formed of a plurality of electrode pads is arranged along the center line in parallel with a pair of the opposing long sides of the semiconductor chip in a rectangular shape. The electrode pads are individually connected to a plurality of external electrodes formed on the surface opposite to the surface of a package substrate, on which the semiconductor chip is mounted, by means of wires or the like.
The above-mentioned electrode pad row on the semiconductor chip is classified into two sub-types. One row consists of command and address (CA) electrode pads, and the other row consists of data (DQ) signals and DQ power supply/DQ ground, i.e., Input/Output (I/O) electrode pads. These sub-types of electrode pad rows are arranged in series in such a way that a row of the I/O electrode pads is located on one end portion of the semiconductor chip and a row of the CA electrode pads is located on the other end portion.
On the other hand, in the external electrodes provided on the package substrate, the external electrodes connected to the I/O electrode pad row are arranged near a pair of the opposing sides of the package substrate in a rectangular shape, that is, they are arranged as divided into two regions. Such an arrangement is provided in order to improve symmetry in a memory chip, to accelerate the speed of the device, and to facilitate wiring in mounting the semiconductor package on the packaging substrate. The arrangement is defined according to standards or the like.
Now, in order to achieve high speed operations in the DDP semiconductor package, it is necessary to prevent the wire length between the semiconductor chip and the external electrodes from varying from chip to chip. This is because the difference in the wire length causes an increase in the input or input/output capacitance of the external electrode having a long wire length as well as causes increased variations in signal delay time (timing), resulting in an obstacle against high speed signaling. Thus, in the case of using the semiconductor chip and the package substrate as described above, it is necessary to design the semiconductor package also taking into consideration the configurations of individual electrode pads and external electrodes. However, no DDP semiconductor packages have been disclosed that are designed by taking into consideration this point. JP 2001-85609 A originally pays no attention to variations in delay time between semiconductor chips. In JP 2009-140995 A, the relative dielectric constant of an encapsulation resin is adjusted to control variations in delay time, but this does not take into account the configurations of the electrode pads and external electrodes.
From the above discussion, the requirement is that, as regards semiconductor devices that have a plurality of semiconductor chips stacked on a substrate, the difference in the wire length between each of the individual semiconductor chips that are to be stacked be reduced and variations in signal delay time be eliminated.